Method of fabricating a contact structure for a raised source/drain MOSFET

ABSTRACT

A method of fabricating a MOSFET device structure, wherein the MOSFET device structure includes field oxide regions, a layer of gate oxide formed on the substrate, oxide sidewall spacers formed on sidewalls of the polysilicon gate, and LDD N- regions formed in the substrate adjacent the field oxide regions and beneath the sidewall spacers. A second layer of polysilicon is deposited over the above-described structure and a chemical mechanical polishing step is performed to self-align the polysilicon source/drain regions to the LDD N- substrate regions. N+ type dopant is then implanted into the gate poly and into the raised source/drain polysilicon regions. Next, a rapid thermal anneal step is performed to activate the N+ implant and to outdiffuse the N+ dopant from the polysilicon raised source/drain regions to form an N+ junction inside the N- LDD source/drain regions. A salicide oxide exclusion mask is then formed to protect the structure with the exception of the polysilicon raised source/drain regions and the polysilicon gate. An amorphization using heavy ion species is then performed to amorphize the surfaces of the gate/source/drain poly regions. A titanium film is then sputter deposited over the entire structure to form the first salicide phase in-situ. Unreacted titanium is then removed using a conventional wet etch and a dielectric layer is deposited and chemically mechanically polished to planarize the structure. The formation of the final titanium salicide phase is performed simultaneously with the densification of the dielectric layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to fabrication techniques for integratedcircuit elements and, in particular, to a process flow for fabricating aMOSFET using fully-salicided raised source/drain regions having contactsformed over isolation oxide.

2. Discussion of the Related Art

FIG. 1 shows a conventional MOSFET transistor 10 fabricated in an activedevice region of a semiconductor wafer substrate, the active deviceregion being defined by field oxide regions in the conventional manner.In fabricating the MOSFET 10, a layer of polysilicon is formed on alayer of thin gate oxide formed on the surface of the substrate activedevice region. The polysilicon layer is then masked and both the exposedpolysilicon and the underlying thin gate oxide are etched to define apolysilicon gate region 12 that is separated from the substrate by thingate oxide 14. A self-aligned implant of N- type dopant then forms lowdensity diffusion (LDD) regions in the substrate as a first phase in theformation of the MOSFET source/drain regions. After the formation ofoxide sidewall spacers (SWS) 15 on the sidewalls of the polysilicon gate12 and the gate oxide 14, a second N+ implant is performed to set theconductivity of the polysilicon gate region 12 to a desired level and tocomplete the N+ source/drain regions 16. Titanium is then deposited onthe exposed upper surfaces of the N+ source/drain regions 16 and thepolysilicon gate 12 and annealed, thereby causing the titanium to reactwith the underlying N+ silicon of the source/drain regions 16 and thedoped polysilicon gate 12 to form titanium salicide 18 on thesesurfaces. A layer of dielectric material 20, typically silicon oxide, isthen formed, contact openings are etched in the dielectric 20 and ametallization layer 22 is formed to provide contacts to the salicide 18on the source/drain regions 16 and on the polysilicon gate 12, therebycompleting the MOSFET structure.

The above-described MOSFET fabrication technique suffers from potentialproblems in the formation of the source/drain regions 16. First,selective growth of the salicide needed for good contacts with themetallization layer requires a reaction between the titanium andunderlying silicon. Therefore, the titanium must be formed on the N+source/drain regions 16, which must be wide enough to accommodate thephotolithographic limitations of the contact opening; this results in awider device. Also, since silicon is consumed in this process, thejunction depth of the N+ source/drain regions 16 is difficult to controland dopant depletion can occur in these regions. Furthermore, formationof the deep, heavily-doped N+ junction for the source/drain regions 16can result in dopant diffusion under the gate region, thereby reducingthe effective channel length of the MOSFET, i.e. the so-called "shortchannel effect." Also, the titanium reacts differently with the singlecrystal source/drain substrate regions 16 and the polysilicon gate 12,resulting in different salicide thicknesses on the source/drain regions16 and the gate 12.

SUMMARY OF THE INVENTION

The present invention provides a MOSFET design that utilizes raisedsource/drain regions in a way that significantly reduces theabove-described problems, including the "short channel effect." The"short channel effect" is reduced because the source/drain N+ junctionis formed inside the N- LDD region by outdiffusing from overlyingpolysilicon, after the N- LDD regions have been formed, during a RapidThermal Anneal (RTA) step. Poly2 is made thinner than poly1 so that allof the poly2 (except the poly2 sidewall material) is consumed duringsalicidation, thereby minimizing parasitic resistance, resulting in highspeed devices. The raised source/drain regions extend over the fieldoxide, thereby allowing the source/drain junction areas to be muchsmaller; therefore, parasitic capacitances associated with the junctionsare greatly reduced, also increasing device speed. The raisedsource/drain flow allows the use of high implant energies and doseswithout much impact on the short channel effect; therefore, dopantdepletion into the titanium salicide is no longer an issue.

Specifically, the present invention provides a method of fabricating aMOSFET device structure in a silicon substrate wherein the MOSFET devicestructure includes planarized trench isolation field oxide regionsformed in the substrate, a layer of gate oxide formed on the substrateto electrically insulate a polysilicon gate from the substrate, oxidesidewall spacers formed on sidewalls of the polysilicon gate and gateoxide, and LDD N- regions formed in the substrate adjacent the fieldoxide regions and beneath the sidewall spacers to define a channelregion in the substrate beneath the polysilicon gate. In accordance withthe method, a second layer of polysilicon is deposited over theabove-described structure and a chemical mechanical polishing step isperformed to self-align the polysilicon source/drain regions to the LDDN- substrate regions. The thickness of the second polysilicon layer isselected such that all of the poly2 on the trench and on the n+substrate is consumed during a subsequent salicidation step, therebycausing minimized parasitic resistance, which results in high speeddevices. N+ type dopant, preferably arsenic, is then implanted into thegate poly and into the raised source/drain poly regions. Next, a rapidthermal anneal step is performed to activate the N+ implant and tooutdiffuse the N+ dopant from the polysilicon raised source/drainregions to form an N+ junction inside the N- LDD source/drain regions. Asalicide oxide exclusion mask is then formed to protect the structure,with the exception of the polysilicon raised source/drain regions andthe polysilicon gate. An amorphization step is then performed usingheavy ion species to amorphize the exposed surfaces of the polysilicongate and the raised poly source/drain regions. A titanium film is thensputter deposited at high temperature over the entire structure to forma first salicide phase (C49) in-situ. Unreacted titanium is then removedusing a conventional wet selective etch and a dielectric layer isdeposited and chemically mechanically polished to planarize thestructure. The formation of the final titanium salicide phase (C54) isperformed simultaneously with the densification of the dielectric layer.Finally, contact holes are opened in the dielectric layer and ametallization structure is deposited and patterned to form contacts withthe titanium salicide.

A better understanding of the features and advantages of the presentinvention will be obtained by reference to the following detaileddescription and accompanying drawings which set forth an illustrativeembodiment in which the principles of the invention are utilized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a partial cross-sectional drawing illustrating a conventionalMOSFET design.

FIGS. 2A-2L are partial cross-sectional drawings illustrating a sequenceof steps for fabricating a raised source/drain MOSFET in accordance withthe concepts of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

A process flow for fabricating a MOSFET device in accordance with theinvention will now be described in conjunction with the partialcross-sectional drawings provided in FIGS. 2A-2L. While no specificprocess parameters are provided, those skilled in the art willappreciate that the concepts of the invention are applicable regardlessof these parameters, which will differ depending upon the specificintegrated circuit structure under manufacture. Those skilled in the artwill also appreciate that, while the following discussion is directed tothe fabrication of N-channel devices, the concepts of the inventionapply to all MOSFET technologies.

The initial fabrication sequence proceeds in a conventional mannerthrough the formation of the trench isolated preliminary MOSFETstructure shown in FIG. 2A. As shown in FIG. 2A, conventional planarizedtrench isolation field oxide regions 100 are formed in a silicon wafer102. Thin gate oxide 104 is formed on the substrate 102 to electricallyinsulate an undoped polysilicon gate 106 from the substrate 102. Oxidesidewall spacers (SWS) 108 are formed on the sidewalls of thepolysilicon gate 106 and the gate oxide 104. Low density diffusion (LDD)N- regions 110 are formed in the substrate 102 adjacent field oxideregions 100 and beneath the oxide sidewall spacers 108 to define aMOSFET channel region in the substrate 102 beneath the polysilicon gate106.

As further shown in FIG. 2A, the first layer of polysilicon can also beutilized in the formation of polysilicon capacitors and thin filmresistors (TFR) on the field oxide regions 100.

Referring to FIG. 2B, a second layer of polysilicon film 112 is thendeposited over the FIG. 2A structure and a chemical mechanical polishing(CMP) step is performed to self-align the polysilicon raisedsource/drain regions 112a to the LDD N- source/drain substrate regions110, resulting in the structure shown in FIG. 2C. It should be notedthat the second polysilicon layer 112 is made thinner than the poly1layer, the thickness being selected such that all of the poly2 formingthe raised source/drain regions 112a is consumed during a subsequentsalicidation step (described below). The minimized parasitic resistanceresulting from complete poly2 consumption produces higher speed devices.

As shown in FIG. 2D, an N+ dopant, preferably arsenic, is then implantedinto the gate polysilicon 106 and into the raised source/drainpolysilicon regions 112a to dope these regions of exposed polysilicon toa desired level.

A rapid thermal processing (RTP) step is then performed to activate theN+ implant and to outdiffuse the N+ dopant from the polysilicon raisedsource/drain regions 112a to form an N+ junction 114 within the N- LDDsource/drain regions 112a, resulting in the structure shown in FIG. 2E.It is noted that, since the N+ junction is formed inside the LDD N-substrate regions 110 by outdiffusing dopant from the raised polyregions 112a, the short channel effects experienced in the prior artprocesses are substantially reduced.

Referring to FIG. 2F, a photoresist mask 116 is then defined over theFIG. 2E structure to pattern a polysilicon thin film resistor (TFR) and,at the same time, to protect the source/drain polysilicon regions 112a.The unwanted polysilicon is then etched away and the photoresist mask116 is removed, resulting in the structure shown in FIG. 2G.

Next, as shown in FIG. 2H, a salicide oxide exclusion mask layer 118 isformed and etched to protect the FIG. 2G structure with the exception ofthe polysilicon raised source/drain regions 112a and the dopedpolysilicon gate 106, as shown in FIG. 2H.

An amorphization step using heavy ion species, e.g., gallium or arsenic,is then performed to amorphize the exposed polysilicon surfaces of thegate 106 and the raised source/drain regions 112a, prior to titaniumdeposition, in order to enhance the salicidation process and to overcomethe narrow line salicidation problems.

Next, as shown in FIG. 2I, a wet cleaning step is performed to removeany surface contamination and titanium film 120 is then deposited overthe entire FIG. 2H structure. The titanium is sputter deposited at400°-500° C. in order to form the first salicide phase (C49) in-situ.The unreacted titanium is then removed using a conventional wetselective etch, resulting in the structure shown in FIG. 2J. Theformation of the final TiSi2 low resistivity phase (C54) is performedsimultaneously with the densification of the first dielectric layer and,therefore, no additional RTP or furnace thermal process is required toform the salicide film. As stated above, all poly2 forming the raisedsource/drain regions 112a is consumed in TiSi2 formation. Densificationis performed in the furnace in nitrogen at about 730 degrees C. forabout 30 minutes.

After removal of the unwanted titanium, a first dielectric layer 124,e.g. silicon oxide, is deposited and a chemical mechanical polishing(CMP) step is performed to planarize the structure, as shown in FIG. 2K.

Finally, as shown in FIG. 2L, contact holes are opened in the dielectriclayer 124 and a metallization structure is deposited to form contactswith the titanium salicide raised source/drain regions 122 and titaniumsalicide 122 on the polysilicon gate 106. In the embodiment of theinvention illustrated in FIG. 2L, the contact metallization includes afirst layer of titanium 126, a second layer of titanium nitride 128 anda final layer of aluminum 130.

It should be understood that various alternatives to the embodiments ofthe invention described herein may be employed in practicing theinvention. It is intended that the following claims define the scope ofthe invention and that methods within the scope of these claims andtheir equivalents be covered thereby.

What is claimed is:
 1. A method of fabricating a MOSFET device structurein a silicon substrate, wherein the MOSFET device structure includesplanarized trench isolation field oxide regions formed in the substrate,a layer of gate oxide formed on the substrate to electrically insulate apolysilicon gate from the substrate, oxide sidewall spacers formed onsidewalls of the polysilicon gate and the gate oxide, LDD N- regionsformed in the substrate adjacent to field oxide regions and beneath thesidewall spacers to define a channel region in the substrate beneath thepolysilicon gate, the method comprising the steps of:forming a secondlayer of polysilicon over the above-defined structure, the thickness ofthe second polysilicon layer being such that the second polysiliconlayer is entirely consumed during a subsequent salicidation step;performing a chemical mechanical polishing step to self-align the secondpolysilicon layer to the LDD N- source/drain substrate regions;implanting N- type dopant into the gate polysilicon and into the raisedsource/drain polysilicon regions; performing a rapid thermal processingstep to activate the N+ implant and to outdiffuse N- type dopant fromthe polysilicon raised source/drain regions to form an N+ junctioninside the N- LDD source/drain regions; amorphizing a surface region ofthe gate polysilicon and the raised source/drain poly regions; sputterdepositing titanium to form a first salicide phase in-situ; removingunreacted titanium; forming a dielectric layer over the resultingstructure formed after said removing unreacted titanium step andperforming a chemical mechanical polishing step to planarize thedielectric layer; densifying the dielectric layer, whereby a finalsalicide phase is obtained; forming contact openings in the densifieddielectric layer to expose the final phase titanium salicide raisedsource/drain regions and the final phase titanium salicide on thepolysilicon gate; and forming a contact metallization layer in thecontact openings to provide electrical contact to the final phasetitanium salicide raised source/drain regions and to the final phasetitanium salicide on the polysilicon gate.
 2. A method as in claim 1 andwherein the step of sputter depositing titanium is peformed at 400-500degrees Celsius.